搜索资源列表
boxingfashengqi
- 波形发生器的源代码，有正弦波，三角波，锯齿波，方波。modelsim仿真，包含testbench仿真代码，testbench用的verilog编写，波形发生器源代码用的VHDL编写。-Waveform generator source code, sine, triangle, sawtooth, square wave. modelsim simulation, testbench simulation code contains, verilog write testbench use, w
ethernet
- opencore上实现以太网mac层的开发版Verilog代码，含英文设计文档与datasheet。可在Modelsim中编译与仿真。-Achieve opencore Ethernet mac layer development version of Verilog code, design documents containing English and datasheet. Can be compiled with the simulation in Modelsim.
cui_mcu
- 微处理器设计（verilog）带测试验证代码modelsim仿真无误 -Microprocessor design (verilog) with modelsim simulation test verification code is correct
adder_carry_chain
- 使用verilog语言实现进位链加法器,quartus下编译，并使用modelsim进行了验证，内含carry_chain.v代码文件以及testbench文件-use verilog language,carry_chain adder
DDS(ok)
- 制作ROM正弦表并填充FPGA内部ROM，通过调用内部数据实现正弦波输出，开发环境quartusii , 语言verilog , 调试通过 ， 附有modelsim调试结果。-Make ROM sine table and fill the ROM internal FPGA, by calling the internal data to achieve the sine wave output, development environment QuartusII, Language Veri
zongbian4
- 基于verilog语言的差分曼彻斯特编码，内包含数据的采集，CRC校验（8位），和编码，输出。附有完整的工程文件。可直接调用modelsim仿真。-Based on differential Manchester encoding verilog language, and contains data collection, CRC check (8), and coding. With complete project file. Modelsim simulation can be call
parallel-to-serial
- 用Verilog语言编程实现并行转串行，并在modelsim中仿真出波形。-programming to realize parallel to serial using Verilog language , and simulating waveform in the modelsim.
serial-to-parallel
- 用Verilog语言编程实现串行转并行，并在modelsim中仿真出波形。-programming to realize serial to parallel using Verilog language , and simulating waveform in the modelsim 。
second-and--minite-and-hour-counter
- 利用Verilog语言实现时分秒计时功能，并用modelsim仿真出波形。-implementate when minutes timing function using Verilog language, and simulating waveform in the modelsim
Sequential-detection-code-101
- 利用Verilog语言实现101序列检测功能，并利用modelsim仿真出波形-Use Verilog language to implementate 101 sequential detection function, and use the modelsim to simulate waveform.
Running-water-light-code
- 利用Verilog实现流水灯，并用按键作为复位信号，最后利用modelsim仿真出波形-Use Verilog to implementate water lights and buttons as a reset signal, finally using modelsim to simulate waveform
FSW
- verilog写的有限状态机（FSW）序列检测，检测到0100_01给出高电平，包含测试文件，Modelsim下仿真成功。-Verilog written finite state machine( FSW) sequence detection, detected 0100_01 given high, including the test file, Modelsim simulation success.
uart_tx
- 基于verilog的uart发送模块，具有可选择的奇偶校验功能，经过modelsim仿真可用。-Based on the uart verilog transmit module with selectable parity function, available through modelsim simulation.
Area-Delay-Power-Efficient-Carry-Select-Adder-usi
- Implementation of IEEE 2015 paper for Area–Delay–Power Efficient Carry-Select Adder using VLSI verilog .The code tested by modelsim and also main program is test.v . If have any trouble mail to anandg.embedd@gmail.com-Implementation of IEEE 2015 pape
EYES_TEST
- 基于FPGA的视力测试。使用的是altera13.0，用MODELSIM仿真，语言为Verilog。-EYES TEST based on FPGA
16QAM
- 可以实现随机序列和16QAM的仿真，verilog语言编程，modelsim和QUARTUS联合仿真(It can realize the simulation of random sequence and 16QAM, Verilog language programming, Modelsim and QUARTUS co simulation.)
071162程序
- 设计一个用于篮球比赛的定时器。要求： （1）定时时间为24秒，按递减方式计时，每隔1秒，定时器减1； （2）定时器的时间用两位数码管显示； （3）设置两个外部控制开关，开关K1控制定时器的直接复位/启动计时，开关K2控制定时器的暂停/连续计时；当定时器递减计时到零（即定时时间到）时，定时器保持零不变，同时发出报警信号，报警信号用一个发光二极管指示。 （4）输入时钟脉冲的频率为50MHz。 （5）用Verilog HDL语言设计，用Modelsim软件做功能仿真，用Quartus II综
LDPC
- LDPC编码的硬件代码,可在modelsim上验证(verilog code for ldpc encode)